1. Technical Field
The invention relates generally to digital circuits, and more particularly relates to programmable/configurable logic arrays. In even greater particularity, the invention relates to NAND and NOR gates.
In an exemplary embodiment, the invention is used in spare gate arrays of a processor to enable logic elements to be formed through metal interconnection only (i.e., without affecting transistor fabrication).
2. Related Art
Logic elements commonly used in the design of digital circuits in general, and processors in particular, include NAND, NOR, XNOR, XOR, and Inverter gates. In CMOS designs, these logic gates are fabricated from p- and n-channel transistors interconnected with metal lines.
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: in a processor design, maximizing the flexibility of using spare gates for correcting design errors through changes in the interconnection of logic elements.
Processors are fabricated from silicon wafers in a series of process steps that can be separated into (a) a base set of process steps that form transistors in the silicon substrate, and (b) a number of metal layers or levels (typically 2-4) that form metal interconnect lines. Approximately 75% of the total fabrication time is devoted to the base set.
Complex integrated circuits such as processors commonly include arrays of spare gates (NAND, NOR, Inverter, etc.) that can be used in fixing function and timing errors using only metal interconnections to and among a selected number of spare gates. Using this debugging approach, the base set transistors do not change--only the metal layers (of course, some functional errors can only be corrected by also changing the base set transistors).
For example, a number of wafers can be started and held after base set fabrication is complete, with only a few risk wafers being fabricated to completion. Parts assembled from the risk wafers can then be tested and, if possible, fixes for functional and timing errors can be identified that involve only the use of spare gates interconnected to the affected logic circuits. Once these fixes are identified, one or more new metal masks can be made, and used in completing fabrication of the wafers held at the metal stage of the process.
To facilitate the spare gate approach to debugging processors or other complex integrated circuits, it would be advantageous to maximize the flexibility of the design of spare gate arrays.